Project Description

AV 107 Phased-Array Radar-Receiver EW-ESM
The AV107 is part of ApisSys’ signal processing solutions based on the VITA 46, VPX standard.
The AV107 is fully compliant with OpenVPX standard, accommodating various communication
protocols such as PCIe, SRIO, 1 Gbit and XAUI 10 Gbit Ethernet, as well as non OpenVPX adopted
standard such as Aurora. The AV107 combines four 12-bit 2.5 Gsps ADCs with ultra high processing power delivered by
Xilinx® Virtex® 7 FPGA, making it ideally suited for fully synchronous multiple channels test and
measurement, Electronic Warfare, Ultra Wideband Radar Receivers or LIDAR applications.
The AV107 features an internal ultra low jitter reference and four independent clock synthesizers.